Testing Boards with Boundary Scan - Principles and Technical Requirements
Boundary Scan is a method of testing electronic assemblies, primarily but not limited to assemblies with a high degree of digital components. The only technical requirement is the existence of at least one component with an interface according to JTAG IEEE 1149.1. The assumption that only components that have such an interface is not true. It is important to have access to non-JTAG components through a JTAG-capable device. Even analog components can be tested if the design has been carefully planned and designed for testability.
Corelis ScanExpress consists of a number of software components used to generate, execute and analyse test plans based on JTAG/Boundary Scan. All software components run in Windows 7, 8, 8.1 or Windows 10.
Typically, the unit under test (UUT) is connected to the PC running ScanExpress through a JTAG controller, available in a variety of form factors. For development of test plans, verification of prototype hardware and desktop use, a USB-connected JTAG controller with a single TAP (Test Access Port) will be a good choice. In a production line, a PCIe, LAN or USB based multi-TAP controller may be the best option. Some of the available JTAG controllers easily integrate into National Instruments test systems under LabView.
If you want to learn more about Boundary Scan or, how to integrate Boundary Scan into an ICT system or, about possibilities and limitations of this fascinating technology, please contact us. We have used Boundary Scan successfully for many years in our own and customer projects. Our experience enables us to assess whether or nor Boundary Scan is a useful option for your testing needs.
Design for Test (Testability)
To analyse the testabilty, especially during development, ScanExpress DFT (Design for Test, P/N Nr. 20300) is very useful. ScanExpress DFT gives the designer hints how to modify the design in order to improve test coverage. Design errors can be detected at an early stage, potentially reducing the number of design spins.
Generation of Test Plans
The generation of test patterns used to execute boundary scan tests is accomplished with ScanExpress TPG (Test Pattern Generator, P/N. 20400). Boundary Scan typically cannot be used to test hardware at speed. That is because pins of a device with a JTAG port are actuated via the so-called scan-chain which inherently does not have the timing of the device under test. There is an interesting article that explains the concept of JTAG/Boundary Scan technology.
However, Corelis has a Boundary Scan extension that remedies the problem of the basic Boundary Scan test method: ScanExpress JET can be used to comfortably test Ethernet, CAN, UART or USB interfaces at speed. Furthermore, SDRAM (DDR, DDR2, DDR3, DDR4) can be tested at system speed, while flash devices, serial flash, EEPROMs and CPLDs can be programmed from within the test procedure. The list of devices supported by JET is constantly being expanded.
Testing multiple Boards
If a combination of boards designed separately requires Boundary Scan testing, ScanExpress Merge (P/N 20196) is required. ScanExpress Merge merges net and component data into a single set of files that can be used by TPG to create test files. ScanExpress Merge is also helpful if a board is tested in combination with a test fixture that also contains JTAG/Boundary Scan capable devices.
Test Execution and Analysis
ScanExpress Runner (P/N 20650) is the central software component used to execute test plans generated with the tools described above. ScanExpress ADO (Advanced Diagnostic Option, P/N 20210) and ScanExpress Viewer (P/N 20315) are add-ons to Runner that generate concise test reports and visualize results. ADO and Viewer are especially helpful when tests are carried out by someone who has little or no background knowledge of the boards being tested, e.g. assembly line personnel.
Testing and Programming I²C and SPI Components
SPI or I²C devices can be tested and programmed even without being connected to a Boundary Scan device if connected to a set of special pins available on the TAP (test access port) of all Corelis JTAG controllers. ScanExpress Programmer JTAG (P/N 20603) and ScanExpress Programmer SPI/I2C (P/N 20601) are the software components used for that purpose.
An interactive Debugger (ScanExpress Debugger, P/N 20409) can be used to analyse problematic circuitry using a C-like script language. There is an interesting video explaining the capabilities of this excellent tool.
JTAG Embedded Test (JET)
ScanExpress JET greatly enhances automatic circuit board testing by extending boundary-scan structural test coverage to virtually every signal on the board that is accessible by an on-board CPU, DSP or microcontroller. ScanExpress JET utilizes proprietary “JTAG Embedded Test” (JET) technology, which uses a processor’s JTAG debug port to download and control native processor code to perform at-speed functional testing of the UUT. JET seamlessly integrates with traditional boundary-scan testing. When running tests using ScanExpress, JET becomes virtually invisible other than it significantly accelerates the test procedure.
Read more about JET.
Integration von ICT und Boundary-Scan
ScanExpress can easily be integrated with traditional ICT systems (Bed-of-Nails, Flying Probes) provided by a number of manufacturers such as SPEA, Takaya, Agilent, Checksum, SEICA, Teradyne and others. Combining Boundary Scan and ICT yields the best possible test coverage while minimizing development efforts and investments.
Boundary Scan Application Support
Corelis and local resellers provide education and hands-on support during all phases of your Boundary Scan projects. Individual support is available on request, e.g. if you need to assess and optimize the test coverage of a board design in progress. Please, do not hesitate to contact us by phone (+49-211-2714630) or using our contact form.
More Information on ScanExpress Boundary Scan tools can be found at https://www.corelis.eu.