Corelis Boundary Scan Board Level Test Systems

Corelis offers an extensive line of ScanExpress software modules that can be custom tailored to create the right boundary-scan package for any user. Corelis’ ScanExpress software is compatible with Microsoft Windows 7, Windows 8/8.1, and Windows 10 as well as all of Corelis’ hardware platforms. Furthermore, DLLs of these functions for integration National Instruments' LabView, LabWindows/CVI, TestStand, Geotest ATEasy, Agilent's VEE, Visual Basic and C++ are available.

ScanExpress software version 9.4 is now available to all users with a current maintenance contract and with new software purchases. Release notes for this version are found further down this page.

 

ScanExpress Software Components for Testing Electronic Assemblies using Boundary-Scan

ScanExpress TPG – Test Pattern Generation ScanExpress TPG™ is an intelligent test pattern generator that enhances the process of boundary-scan automation at an exceptional level of ease of use. ScanExpress TPG automatically generates test patterns that facilitate pin-level fault detection and isolation of all boundary-scan testable nets on a printed circuit board (PCB). ScanExpress TPG also creates test vectors to detect faults on pins of non-JTAG components such as clusters and memories that are accessible by IEEE-1149.1 compatible devices.

ScanExpress JET – JTAG Embedded TestScanExpress JET™ represents state-of-the-art in automatic circuit board testing by extending boundary-scan structural test coverage to virtually every signal on the board that is accessible by an on-board CPU. ScanExpress JET utilizes proprietary “JTAG Embedded Test” (JET) technology, which uses a processor’s JTAG debug port to download and control native processor code to perform at-speed functional testing of the UUT.

ScanExpress DFT Analyzer – Design for Testability MetricsScanExpress DFT™ Analyzer is able to accurately calculate the test coverage of boards and systems that include a mix of both boundary-scan and non-boundary-scan devices. The software additionally helps development engineers detect low coverage areas on their designs allowing them to make decisions on increasing fault coverage before the board is sent for layout.
Test Execution System

ScanExpress Runner – Test Program ExecutionScanExpress Runner™ provides a runtime executive environment that is friendly for design, production, and field service. ScanExpress Runner allows users to execute a test sequence or individual test steps based on test patterns generated with ScanExpress TPG and/or ScanExpress JET. To identify failures - if any -  a truth table diagnostic display is generated for further inspection.


ScanExpress Runner Gang – High Volume Test Program ExecutionScanExpress Runner Gang™ is the workhorse software piece to perform parallel gang testing and In-System Programming of CPLDs and Flash devices. This solution is fully concurrent and allows simultaneous testing of multiple boards using a single PC and a single operator. ScanExpress Runner Gang addresses high-throughput boundary-scan applications including high-volume production.

 

view iconScanExpress Viewer™ is a powerful graphical fault identification system that helps to isolate the source and location of faults encountered during boundary-scan test of printed circuit board assemblies. The device and pin location capabilities provide test operators the immediate board location of the faulty pin or net.

 

SoftwareScanExpress ADO – Advanced Diagnostics

ScanExpress ADO™ is an add-on option for the ScanExpress Runner and ScanExpress Runner Gang execution environments. The Advanced Diagnostics Option automates test vector analysis by intelligently deciphering standard truth table diagnostic information and presenting specific fault information to the user in a detailed verbose format.

 

ScanExpress Merge – System Level Testing across AssembliesScanExpress Merge™ makes system-level boundary-scan test development a snap by automatically combining multiple target assemblies into a single boundary-scan compatible target system. The tool provides automatic handling for each board netlist, scan-chain, and interconnect information.

 

ScanExpress JTAG Debugger – Interactive DebuggingScanExpress JTAG Debugger™ provides a simple, stand-alone environment for complete pin control over any boundary-scan device. The interactive graphical user interface lets users mimic the functionality of a logic analyzer by observing all boundary-scan controllable inputs while also providing the capability to drive output pins to specific logic states. The software can be used to quickly apply patterns to specific areas of a board giving immediate feedback when faults are detected.

Boundary-Scan In-System Programming (ISP) Tools

ScanExpress JTAG Programmer – In-Circuit Programming ToolScanExpress JTAG Programmer™ is a universal in-circuit programming tool that can program and verify Flash memories, serial EEPROMs, CPLDs, FPGAs, and other programmable logic devices. Programming methods include JTAG, I2C, SPI, and Target Assisted. The extensive device library includes chip manufacturers such as Altera, Cypress, Micron, Spansion, Intel, Microchip, ST Microelectronics, Texas Instruments, Xilinx, and many more.

 

ScanExpress Flash Generator – Flash Programming File Generation ToolThe ScanExpress Flash Generator™ creates a Board File, which is used to provide ScanExpress Programmer (or other compatible applications) with the necessary information to program a given target board configuration. ScanExpress Flash Generator can be used as a standalone utility or as a module integrated with the ScanExpress TPG environment.

 


ScanExpress Version 9.4.x Release Notes

Corelis ScanExpress applications have been updated with the latest features, enhancements, and device support.
ScanExpress Runner now includes an asynchronous API for integration with third party applications. The asynchronous execution functions allow applications to integrate ScanExpress Runner functionality without having to wait for execution to finish—applications can now begin execution and then poll to determine current status or abort the current execution.

The new functions are:
AsyncAbort() Aborts asynchronous Test Plan execution.
AsyncGetStatus() Retrieves the current status and completion percentage of asynchronous Test Plan execution.
AsyncRunTestPlan() Runs the currently loaded Test Plan asynchronously, returning immediately.
ScanExpress Runner Diagnostic & Logging Improvements

ScanExpress Runner now includes full test plan and test step path information in the test log file for improved traceability. Additionally, flash manufacturer and device ID information will now be included in diagnostics and test logs when Device ID tests pass. Finally, we’ve improved JAM/STAPL diagnostics to include additional checksum data when available.
ScanExpress Runner Gang USB-1149.1/4E

ScanExpress Runner Gang can now utilize USB-1149.1/4E and QuadTAP/CFM hardware for concurrent test execution. Gang (concurrent) tests on up to 4 TAPs can now be run on the benchtop with USB-1149.1/4E hardware or integrated into Teradyne testers with the QuadTAP/CFM and expander cards.
ScanExpress JET CPU Support & Improvements

ScanExpress JET supports many microcontrollers, FPGAs, and SoCs, e.g. Infineon's Aurix, Nvidia's Tegra K1, NXP's CorIQ P2, Xilinx Zynq, and Mobileye's EyeQ3 devices. Starting with version 9.4 ScanExpress JET supports Marvell OCTEON III CN7200 Multi-Core MIPS64 Processors and Texas Instruments TMS320C6748 DSP Processors. Each new processor support package includes base RAM and NOR flash tests and programming support. Please contact Corelis Sales for pricing and availability. Additionally, Ethernet loopback tests are now included for NXP i.MX6 Applications Processors.

Corelis ScanExpress 9.4 is now available free for customers under maintenance. Please, inquire for more information.


 

JTAG Controllers for Board Level Testing

A wide selection of JTAG (boundary-scan) hardware controllers is available from Corelis, including PCI, PCI Express, USB 2.0, Ethernet/LAN, PXI/cPCI and VXI, with price and performance to meet your specific requirements. For performance critical JTAG applications, Corelis offers boundary-scan controllers that operate at up to 100MHz sustained TCK frequency, enabling fast board JTAG interconnect testing and JTAG programming of flash memories at their maximum theoretical speed. From single-TAP JTAG-controllers for development and test bench use to multi-TAP controllers for inline volume production testing, there is a suitable controller for every purpose.

Corelis offers support for a variety of devices and instruments from third-parties in an effort to provide existing test platforms comprehensive JTAG test execution with Corelis ScanExpress software products. Supported instruments include National Instruments PXI-655x HSDIO and Teradyne Di-Series modules. Corelis also provides support for JTAG testing with FTDI FT2232 ICs embedded on a unit under test (UUT).

For more information on JTAG technology, please check out the JTAG tutorial. You may also be interested in how to debug a dead board.

 

Analysers / Exercisers for I²C and SMBus

The high performance CAS-1000 I2C/E I2C/SMBus bus analyzer and exerciser is an enhanced model targeted towards IC verification and parametric testing in I²C and SMBus topologies. The CAS-1000-I2C/E hardware provides more advanced features such as master and slave emulation, bus specification validation, bus parameter measurement, glitch injection, clock stretching, and adjustable timing skew. In conjunction with Corelis ScanExpress software, the CAS-1000 controller can be used for Boundary Scan testing of complete boards as well as for (interconnect test, etc.) as well as for in-system-programming of Flash memory and CPLDs.

More information on Corelis Boundary Scan products, consulting and training is available on request.

Note: If in doubt which products or product combination suits your testing and programming needs, please, feel free to contact us or our European representatives.