Benefits of Boundary-Scan for PCB Assembly Testing
The Benefits of Boundary-Scan for PCB Assembly Testing
Businesses often categorize PCB assembly testing tools and methods as an expense rather than something that adds value to the end product. So, why should companies bother with PCB assembly testing?
Conducting product testing on printed circuit boards (PCBs) has the potential to become costly. Because of this, it’s easy for businesses to view PCB assembly testing as an expense without much value.
So, why test?
The answer is two-fold. First, manufacturers can’t guarantee product quality without testing. Second, when done correctly, testing saves companies time and money in the long term. Inadequate testing can result in inferior quality products getting shipped to end customers, leading to warranty repairs, field failures that require replacement, an inferior product image, and—depending on the industry—even incite potential lawsuits.
On the other hand, adequate testing doesn’t mean that every product requires 100% test coverage. The costs of the tests necessary to achieve the last few points toward 100% are often not only unnecessary, but costly to a point where both production costs and the retail cost of the product can increase exponentially.
It’s essential to assess the optimum amount of testing for a given product and industry to maintain a high-quality product while also limiting the overall cost of test. For example, military and aerospace products require a significantly higher investment in test when compared to other industries due to the nature of their mission-critical operation. On the other end of this spectrum, however, lower-cost consumer electronic products, where some amount of product defects may be acceptable, typically requires a smaller test investment.
Finding Optimum Testing Coverage
Three main elements of a PCB assembly are evaluated during testing: structural devices, structural connections, and functional connections. These elements are assessed using a combination of popular visual, electrical, and functional testing methods, including automated optical inspection (AOI), automated X-ray inspection (AXI), in-circuit testing (ICT), JTAG boundary-scan, and customized test software.
Many PCB assembly manufacturers use an approach known as PCOLA/SOQ/FAM when evaluating the effectiveness of test systems for their products. This approach defines a defect-spectrum of fault categories for assembled PCBs that can be used by test engineers to calculate a score for defect coverage. The “PCOLA” segment of the test evaluates the structural devices of a populated PCB using visual testing methods. This portion of the test looks at presence, correctness, orientation, live, and alignment.
• Presence: Does the component exist? Is it present?
• Correctness: Is the correct component installed?
• Orientation: Is the orientation of the component correct?
• Live: Is the component operational? Does the component respond to stimulus?
• Alignment: Is the alignment of the component skewed or within acceptable tolerance?
The “SOQ” segment uses electrical testing methods to evaluate shorts, opens, and quality. These are connectivity tests to ensure an accurate electrical connection between components as well as identify the quality of those connections.
• Shorts: Is the component connection point incorrectly connected to another connection point?
• Opens: Is the component connection missing a connection to another connection point?
• Quality: Does the component connection conform to quality standards?
Functional testing, which is the last type of test process in the PCOLA/SOQ/FAM defect spectrum, evaluates features, at-speed, and measurement. These tests ensure that components and connections in the system are functioning as expected and measure performance against known benchmarks.
• Features: Is the component feature present?
• At-Speed: Can the component or connection be tested at minimum and maximum speeds?
• Measurement: Can component or connection attributes be measured?
While several testing methods are available, test budgets necessitate manufacturers to select test methods that provide comprehensive coverage of the PCOLA/SOQ/FAM spectrum. A breakdown of the PCOLA/SOQ/FAM approach and the applicable tests can be seen in the table below:
When making decisions about testing and achieving the optimum amount of coverage, it’s important to consider which test methods include a significant portion of the PCOLA/SOQ/FAM defect-spectrum. JTAG boundary-scan, a method for testing PCBs when physical test access is limited, is ideal for this reason. Unlike other methods, boundary-scan can perform tests covering a significant portion of the PCOLA/SOQ/FAM spectrum. Because of this, JTAG boundary-scan testing is often able to reduce or even eliminate the need for additional structural testing methods and equipment:
Other Benefits of JTAG Boundary-Scan Testing
JTAG boundary-scan testing provides a high-level of coverage for PCB testing, but it also offers cost savings in other ways. Equipment acquisition, test procedure development, training, and labor expenses are among the inherent costs of performing boundary-scan testing.
These costs may sound expensive, but performing boundary-scan testing is actually less costly than using popular PCB testing methods like ICT. In fact, in addition to the cost of equipment acquisitions, procedure development, and training and labor, ICT requires test fixture development and equipment maintenance, which are costs that aren’t incurred in boundary-scan testing.
Additional benefits to consider are:
• Significant product yield increase
• Reusable test patterns
• Reduced test time
• Reduced time to market
The Bottom Line
When selecting testing methods, manufacturers must take numerous factors into consideration, including when each method can be deployed, equipment and maintenance costs, and the amount of defect-spectrum coverage. Among the most popular test methods, JTAG boundary-scan testing stands out as the most affordable and versatile option to best meet these factors.
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Boundary Scan is a method of testing electronic assemblies, primarily but not limited to assemblies with a high degree of digital components. The only technical requirement is the existence of at least one component with an interface according to 
ScanExpress TPG™ is an intelligent test pattern generator that enhances the process of boundary-scan automation at an exceptional level of ease of use. ScanExpress TPG automatically generates test patterns that facilitate pin-level fault detection and isolation of all boundary-scan testable nets on a printed circuit board (PCB). ScanExpress TPG also creates test vectors to detect faults on pins of non-JTAG components such as clusters and memories that are accessible by IEEE-1149.1 compatible devices.
ScanExpress JET™ represents state-of-the-art in automatic circuit board testing by extending boundary-scan structural test coverage to virtually every signal on the board that is accessible by an on-board CPU. ScanExpress JET utilizes proprietary “JTAG Embedded Test” (JET) technology, which uses a processor’s JTAG debug port to download and control native processor code to perform at-speed functional testing of the UUT.
ScanExpress DFT™ Analyzer is able to accurately calculate the test coverage of boards and systems that include a mix of both boundary-scan and non-boundary-scan devices. The software additionally helps development engineers detect low coverage areas on their designs allowing them to make decisions on increasing fault coverage before the board is sent for layout.
ScanExpress Runner™ provides a runtime executive environment that is friendly for design, production, and field service. ScanExpress Runner allows users to execute a test sequence or individual test steps based on test patterns generated with ScanExpress TPG and/or ScanExpress JET. To identify failures - if any - a truth table diagnostic display is generated for further inspection.
ScanExpress Runner Gang™ is the workhorse software piece to perform parallel gang testing and In-System Programming of CPLDs and Flash devices. This solution is fully concurrent and allows simultaneous testing of multiple boards using a single PC and a single operator. ScanExpress Runner Gang addresses high-throughput boundary-scan applications including high-volume production.
ScanExpress Viewer™ is a powerful graphical fault identification system that helps to isolate the source and location of faults encountered during boundary-scan test of printed circuit board assemblies. The device and pin location capabilities provide test operators the immediate board location of the faulty pin or net.
ScanExpress Merge™ makes system-level boundary-scan test development a snap by automatically combining multiple target assemblies into a single boundary-scan compatible target system. The tool provides automatic handling for each board netlist, scan-chain, and interconnect information.
ScanExpress JTAG Debugger™ provides a simple, stand-alone environment for complete pin control over any boundary-scan device. The interactive graphical user interface lets users mimic the functionality of a logic analyzer by observing all boundary-scan controllable inputs while also providing the capability to drive output pins to specific logic states. The software can be used to quickly apply patterns to specific areas of a board giving immediate feedback when faults are detected.
ScanExpress JTAG Programmer™ is a universal in-circuit programming tool that can program and verify Flash memories, serial EEPROMs, CPLDs, FPGAs, and other programmable logic devices. Programming methods include JTAG, I2C, SPI, and Target Assisted. The extensive device library includes chip manufacturers such as Altera, Cypress, Micron, Spansion, Intel, Microchip, ST Microelectronics, Texas Instruments, Xilinx, and many more.
The ScanExpress Flash Generator™ creates a Board File, which is used to provide ScanExpress Programmer (or other compatible applications) with the necessary information to program a given target board configuration. ScanExpress Flash Generator can be used as a standalone utility or as a module integrated with the ScanExpress TPG environment.